1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to an apparatus and a method for detecting faulty cells in a semiconductor memory device.
2. Description of the Related Art
Due to the development of very large scale integration (VLSI) technology, the integration density and the operating speed of chips is increasing. Also, in order to reduce the area of chips, a narrow line width technology has been adopted. As a result, more cells can be integrated in the same chip area. Techniques for testing whether faults exist in chips have been a matter of concern as VLSI technology has developed.
Various causes of faults in a VLSI circuit can be simply modeled. Among fault models of VLSI circuits, the most common one is a stuck-at fault model. Using the stuck-at fault model, it is possible to detect a logic operation fault, where the logic level of a node in the circuit is "stuck at" a logic "0" or "1". However, it is difficult to detect a parametric fault or a transient fault, which prohibit the normal operation of chips by affecting delay time, using the stuck-at fault model. Therefore, a current test is used in order to detect these faults.
It is possible to detect whether faults exist in the circuit by the current test using a phenomenon in which excessive current is generated in the circuit due to the parametric fault or the transient fault. The current test can be classified as an on-chip test or an off-chip test, depending upon whether a current detector for detecting current in the circuit is loaded into the chip. In the on-chip test, it is determined by the built-in current detector whether the chip is faulty. In the off-chip test, it is determined whether the chip is faulty using a current detector included in external test equipment.
However, in the case of the off-chip test performed using the test equipment, current generated in the tested chip is transmitted to the test equipment through the output pin of the tested chip. Accordingly, current resolution may deteriorate. Also, when the operating speed of the test equipment is lower than the operating speed of the tested chip, current detection speed decreases. Accordingly it takes longer to test the chip.
The on-chip test is mainly used for a test for detecting faulty cells in a semiconductor memory device. In the case of the on-chip test, since the current detector is integrated into the tested chip, current is analyzed in the tested chip and the analysis result is output. Therefore, the degree of correctness in detecting faults increases. Also, since the test speed of the on-chip test corresponds to the operating speed of the tested chip, the test speed significantly increases. However, in the on-chip test, the layout area of the tested chip increases and the normal operating speed of the chip may decrease, due to the integrated current detector.
Therefore, a minimum number of current detectors must be used when the circuit is designed for performing the on-chip test. According to the conventional circuit for detecting faulty cells in the semiconductor memory device, the number of current detectors is restricted. As a result, although it is possible to detect whether faulty cells exist, it is difficult to detect the correct positions of the faulty cells.